Moore's Law could be about to shift into hyperdrive as a new 7-nanometer-square transistor allows chipmakers to cram more memory onto their semiconductors.
The Room Temperature Single Electron MOS Memory transistor, developed by Stephen Chou, professor of electrical engineering at the University of Minnesota, uses one electron to represent a binary bit of information. By limiting the number of electrons - existing devices use plus or minus 30,000 per bit - the component could shrink in size.
"This will more than triple a processor's speed," claims Chou. Manufacturers using the new technology might someday be able to squeeze a billion transistors in the same space that, in today's Pentium, is occupied by a mere 5.5 million.
But will chips keep getting smaller? Chou doubts it. But he does see an opening elsewhere in chip real estate - keep an eye on multilevel chips.
ELECTRIC WORD
No Two-Bit Chip
